Display substrate and method of manufacturing the same

ABSTRACT

In a manufacturing method of a display substrate according to one or more embodiments, a plurality of thin films are patterned by using a photoresist film pattern having different thicknesses in each area on a substrate as etch masks. The photoresist film pattern may be etch-backed at least twice during the manufacturing process of the display substrate and may be used as the etch mask for patterns having shapes different from each other. Accordingly, the number of processes for manufacturing the mask patterns, which may be formed by a photolithography method in order to pattern the thin films formed on the substrate, may be reduced.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/203,859 filed on Sep. 3, 2008, which claims priority to and benefitfrom Korean Patent Application No. 10-2007-0126784 filed on Dec. 7,2007, the contents of which are herein incorporated by reference intheir entirety.

BACKGROUND

1. Technical Field

Embodiments of the present invention generally relate to a displaysubstrate and a method of manufacturing the display substrate.

2. Description of the Related Art

In general, a display apparatus that displays an image includes adisplay substrate. A plurality of pixel areas that displays an image isdefined in the display substrate. Each pixel area includes a thin filmtransistor and a pixel electrode electrically connected to the thin filmtransistor.

The thin film transistor includes a semiconductor pattern to selectivelyprovide the pixel electrode with a pixel voltage according to a voltageapplied to a gate electrode thereof. The semiconductor pattern includesan organic semiconductor such as amorphous silicon or pentacene.

When the semiconductor pattern includes an organic semiconductor, theorganic semiconductor is formed on the display substrate through aninkjet method. When forming the organic semiconductor on the displaysubstrate through the inkjet method, precise patterning of the organicsemiconductor is difficult. Thus, a technology has been proposed forforming a bank pattern on the display substrate and introducing theorganic semiconductor into an opening of the bank pattern before formingthe organic semiconductor on the display substrate.

However, when forming the organic semiconductor on the display substrateby using the bank pattern, this additional process of forming the bankpattern would be required. Thus, the number of processes for the displaysubstrate increases, thereby increasing the manufacturing cost of thedisplay substrate

SUMMARY

Embodiments of the present invention generally provide a displayapparatus having a simplified structure and reduced manufacturing costand a method of manufacturing the display substrate.

In one aspect of an embodiment of the present invention, a method ofmanufacturing a display substrate is provided as follows. A gateelectrode is formed on a substrate and a gate insulating layer is formedon the substrate to cover the gate electrode. Then, first and secondconductive layers are sequentially formed on the gate insulating layerto form a source-drain layer, and a first insulating layer pattern isformed on the source-drain layer. A preliminary source-drain layer isformed by patterning the source-drain layer by using the firstinsulating layer pattern and a second insulating layer pattern, which isformed by primarily etching the first insulating layer pattern, as etchmasks, respectively. A third insulating layer pattern is formed bysecondarily etching the second insulating layer pattern, and a surfacetreatment is performed relative to the substrate. A source electrode anda drain electrode, which are spaced apart from each other, are formed bypatterning the preliminary source-drain layer, and an organicsemiconductor layer is formed on the source and drain electrodes. Then,a pixel electrode electrically connected to the drain electrode isformed on the substrate.

In another aspect of an embodiment of the present invention, a displaysubstrate includes: a substrate in which a pixel area is defined, a gateline formed on the substrate, a gate insulating layer formed on the gateline to cover the gate line, a data line insulated from the gate linewhile crossing the gate line, and defining the pixel area in combinationwith the gate line, a gate electrode branching from the gate line, asource electrode branching from the data line, a drain electrode spacedapart from the source electrode, an organic semiconductor layer formedon the source electrode and the drain electrode, and a pixel electrodeformed on the substrate in correspondence with the pixel area, andelectrically connected to the drain electrode. In order to easily formthe organic semiconductor layer on the gate insulating layer, the gateinsulating layer has a different surface energy in each area. Accordingto one or more embodiments, a portion of the gate insulating layercorresponding to an area in which the organic semiconductor layer isformed, has a surface energy greater than a surface energy of the gateinsulating layer corresponding to an area in which the organicsemiconductor layer is not formed.

According to the above description of one or more embodiments, whenforming the organic semiconductor layer through an inkjet method, a bankpattern used for the organic semiconductor layer may be omitted.Accordingly, a photolithography process for the bank pattern may beomitted, so that the manufacturing process of the display substrate maybe simplified and the manufacturing cost of the display substrate may bereduced.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of one or more embodiments of the presentinvention will become readily apparent by reference to the followingdetailed description when considered in conjunction with theaccompanying drawings wherein:

FIGS. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are plan views illustratinga method of manufacturing a display substrate according to one or moreexemplary embodiments of the present invention;

FIGS. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B and 9B are cross-sectional viewstaken along line I-I′ shown in FIGS. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A and9A, respectively, according to one or more embodiments;

FIG. 10 is a sectional view illustrating a method of forming the firstinsulating layer pattern shown in FIG. 3B according to an embodiment; an

FIG. 11 is a sectional view illustrating a method of forming the firstinsulating layer pattern shown in FIG. 3B according to another exemplaryembodiment of the present invention.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be explained indetail with reference to the accompanying drawings. However, the scopeof the present invention is not limited to such embodiments and thepresent invention may be realized in various forms. Embodiments of thepresent invention are defined only by the scope of the appended claims.In addition, the size of layers and regions shown in the drawings may besimplified or magnified for the purpose of clear explanation. Inaddition, the same reference numerals are used to designate the sameelements throughout the drawings.

FIGS. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are plan views illustratinga method of manufacturing a display substrate according to one or moreexemplary embodiments of the present invention, and FIGS. 1B, 2B, 3B,4B, 5B, 6B, 7B, 8B and 9B are cross-sectional views taken along lineI-I′ shown in FIGS. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A, respectively,according to one or more embodiments.

Referring to FIGS. 1A and 1B, a gate line GL and a gate electrode GEbranching from the gate line GL are formed on a substrate 10. Afterforming the gate line GL and the gate electrode GE on the substrate 10,a gate insulating layer 20 that covers the gate line GL and the gateelectrode GE is formed on the substrate 10. The gate line GL and thegate electrode GE may be made by forming a conductive layer (not shown)on the substrate 10 and patterning the conductive layer.

In the present exemplary embodiment, the substrate 10 may include atransparent glass base material. However, the substrate 10 may alsoinclude other transparent and flexible materials, e.g. plastic.

Referring to FIGS. 2A and 2B, a first conductive layer 31 and a secondconductive layer 34 are sequentially formed on the substrate 10 to forma source-drain layer 37. The first and second conductive layers 31 and34 are sequentially formed on the substrate 10 because a surfacetreatment process for the substrate 10 is performed between a patterningprocess for the first conductive layer 31 and a patterning process forthe second conductive layer 34. Detailed descriptions of the surfacetreatment process according to one or more embodiments will be givenwith reference to FIGS. 5A and 5B.

Referring to FIGS. 2B, 3A and 3B, a first insulating layer pattern 40 isformed on the source-drain layer 37. The first insulating layer pattern40 is removed corresponding to a first area A1 to form an opening. Thefirst insulating layer pattern 40 may have thicknesses that aredifferent from each other in the second to fourth areas A2 to A4,respectively. According to an embodiment, the first insulating layerpattern 40 has a first thickness t1 in the second area A2, a secondthickness t2 greater than the first thickness t1 in the third area A3,and a third thickness t3 greater than the second thickness t2 in thefourth area A4.

The first insulating layer pattern 40 may be formed by forming aphotoresist film on the substrate 10, exposing the photoresist film byusing a photomask formed with a slit pattern and a transflective member,and developing the photoresist film. Furthermore, the first insulatinglayer pattern 40 may also be formed through an imprint scheme, in whichan imprint resin layer is formed on the substrate 10, and then theimprint resin layer is pressed by a mold. These two methods of formingthe first insulating layer pattern 40 according to one or moreembodiments will be described in more detail with reference to FIGS. 10and 11.

FIG. 10 is a sectional view illustrating a method of forming the firstinsulating layer pattern 40 according to an embodiment. Referring toFIG. 10, a photoresist film 45 having positive photosensitivity isformed on the substrate 10 on which the gate electrode GE, the gateinsulating layer 20 and the source-drain layer 37 are formed.

After forming the photoresist film 45 on the substrate 10, a photomask110 is aligned above the substrate 10 such that the photomask 110 facesthe substrate 10, and source light L0 is irradiated onto the photoresistfilm 45 to expose the photoresist film 45.

A first part of the photomask 110 corresponding to the first area A1 isopen or prepared in the form of a transmitting member 101, a second partof the photomask 110 corresponding to the second area A2 is prepared inthe form of a transflective member 48, a third part of the photomask 110corresponding to the third area A3 is prepared in the form of thetransflective member 48 and a slit pattern 103, and a fourth part of thephotomask 110 corresponding to the fourth area A4 is prepared in theform of a light blocking member 102.

Accordingly, the first light L1 irradiated onto the first area A1 of thephotoresist film 45 has a first light amount, the second light L2irradiated onto the second area A2 has a second light amount smallerthan the first light amount, the third light L3 irradiated onto thethird area A3 has a third light amount smaller than the second lightamount, and light is not irradiated onto the fourth area A4.

As the exposed photoresist film 45 is developed, the photoresist film 45is partially removed according to the amount of the irradiated light.According to an embodiment, the photoresist film 45 may be completelyremoved from the first area A1, the photoresist film 45 has a firstthickness t1 in the second area A2, the photoresist film 45 has a secondthickness t2 greater than the first thickness t1 in the third area A3,and the photoresist film 45 has a third thickness t3 greater than thesecond thickness t2 in the fourth area A4.

FIG. 11 is a sectional view illustrating a method of forming the firstinsulating layer pattern 40 according to another exemplary embodiment ofthe present invention. Referring to FIG. 11, after forming a photoresistfilm having photosensitivity on the substrate 10 on which the gateelectrode GE, the gate insulating layer 20 and the source-drain layer 37are formed, the first insulating layer pattern 40 may be formed byimprinting the photoresist film using a mold 120.

Although not shown in FIG. 11, after forming the first insulating layerpattern 40, the first insulating layer pattern 40 may be cured byirradiating light onto the first insulating layer pattern 40, then themold 120 may be separated from the substrate 10 so that photoresist filmpatterns having thicknesses different from each other may be formed ineach area.

Referring again to FIGS. 2B, 3A and 3B, after forming the firstinsulating layer pattern 40 on the substrate 10, the source-drain layer37 is etched using the first insulating layer pattern 40 as an etchmask. Thus, the source-drain layer corresponding to the first area A1 isremoved to form a preliminary source-drain pattern 38 that includes adata line, and first and second preliminary conductive patterns 32 and35, and is located on the same plane with the first insulating layerpattern 40.

Referring to FIGS. 3B, 4A and 4B, a second insulating layer pattern 41may be formed by performing a first etch-back process relative to thefirst insulating layer pattern 40. The second insulating layer pattern41 has fourth and fifth thicknesses t4 and t5 in the third and fourthareas A3 and A4, respectively. The second insulating layer pattern 41 iscompletely removed from the first and second areas A1 and A2.

The first insulating layer pattern 40 is etched by the first thicknesst1 through the first etch-back process. Thus, the fourth thickness t4 isidentical to the difference between the second thickness t2 and thefirst thickness t1, and the fifth thickness t5 is identical to thedifference between the third thickness t3 and the first thickness t1.

After forming the second insulating layer pattern 41 on the substrate10, the second preliminary conductive pattern 35 corresponding to thesecond area A2 may be etched by using the second insulating layerpattern 41 as an etch mask to form a top preliminary source electrode 36a and a top preliminary drain electrode 36 b.

Referring to FIGS. 4B, 5A and 5B, a third insulating layer pattern 42may be formed by performing a second etch-back process relative to thesecond insulating layer pattern 41. The third insulating layer pattern42 has a sixth thickness t6 in the fourth area A4, and is completelyremoved from the first to third areas A1 to A3.

The second insulating layer pattern 41 is etched by the fourth thicknesst4 through the second etch-back process. Thus, the sixth thickness t6 isidentical to the difference between the fifth thickness t5 and thefourth thickness t4.

After forming the third insulating layer pattern 42 on the substrate 10,the substrate 10 may be subjected to a surface treatment process toreduce the surface energy of the outermost thin film exposed on thesubstrate 10. In the present exemplary embodiment, the surface treatmentprocess for the substrate 10 may include plasma treatment.

The plasma treatment may increase or decrease the surface energy of thesubstrate 10 exposed to the exterior. Increasing or decreasing thesurface energy of the substrate 10 exposed to the exterior through theplasma treatment may be determined according to the type of reaction gasused for the plasma treatment. According to the present exemplaryembodiment, the plasma treatment may reduce the surface energy of thesubstrate 10 exposed to the exterior by using a reaction gas containingfluorine such as CF₄.

Since the third insulating layer pattern 42 is exposed to the exteriorafter the surface treatment is completed, the surface energy of thethird insulating layer pattern 42 may be reduced through, for example,the plasma treatment. Furthermore, after the surface treatment iscompleted, the gate insulating layer 20 may have a different surfaceenergy in each area. According to an embodiment, a portion of the gateinsulating layer 20 overlapping with the first preliminary conductivepattern 32 may have a surface energy greater than that of a portion ofthe gate insulating layer 20 exposed to the exterior.

Referring to FIGS. 5B, 6A and 6B, the first preliminary conductivepattern 32 corresponding to the second area A2 may be etched using thetop preliminary source electrode 36 a and the top preliminary drainelectrode 36 b as etch masks, thereby forming a bottom source electrode33 a and a bottom drain electrode 33 b while being spaced apart fromeach other.

Furthermore, the first preliminary conductive pattern 32 correspondingto the second area A2 may be etched to expose to the exterior a portionof the gate insulating layer 20, which corresponds to the second areaA2. The exposed portion of the gate insulating layer 20 is referred toas a non-surface treatment section 21 since the non-surface treatmentsection 21 is not surface-treated through the surface treatment process.The non-surface treatment section 21 has a surface energy greater thanthat of a peripheral section such as the third insulating layer pattern42.

If the non-surface treatment section 21 has a surface energy greaterthan that of a peripheral section, an organic, for example,semiconductor layer (reference number 50 of FIG. 8B) may be easilyformed on the second and third areas A2 and A3 using an inkjet method.The surface energy of the non-surface treatment section 21 according toan embodiment will be described in detail with reference to FIGS. 8A and8B.

Referring to FIGS. 6B, 7A and 7B, the top preliminary source electrode36 a and the top preliminary drain electrode 36 b corresponding to thethird area A3 are patterned using the third insulating layer pattern 42,respectively, to form a top source electrode 36 a′ and a top drainelectrode 36 b′, thereby completing fabrication of a source electrode SEincluding the top source electrode 36 a′ and the bottom source electrode33 a, and a drain electrode DE including the top drain electrode 36 b′and the bottom drain electrode 33 b.

The reason that the top preliminary source electrode 36 a and the toppreliminary drain electrode 36 b that correspond to the third area A3are removed is because the organic semiconductor layer has a lowercontact resistance relative to the bottom source electrode 33 a and thebottom drain electrode 33 b than the top source electrode 36 a′ and thetop drain electrode 36 b′.

For example, when the bottom source electrode 33 a and the bottom drainelectrode 33 b include indium tin oxide (ITO) having a low contactresistance relative to the organic semiconductor layer, the organicsemiconductor layer may be electrically connected to the bottom sourceelectrode 33 a and the bottom drain electrode 33 b by removing the toppreliminary source electrode 36 a and the top preliminary drainelectrode 36 b corresponding to the third area A3.

When the top source electrode 36 a′ and the top drain electrode 36 b′include a conductor having a low contact resistance relative to theorganic semiconductor layer, the process of removing the top preliminarysource electrode 36 a and the top preliminary drain electrode 36 bcorresponding to the third area A3 may also be omitted.

Referring to FIGS. 8A and 8B, an organic semiconductor layer 50 may beformed on the second and third areas A2 and A3 by spraying an organicsemiconductor 51 toward the second and third areas A2 and A3 through adispenser 52, thereby completing fabrication of an organic thin filmtransistor T that includes the source electrode SE, the gate electrodeGE, the drain electrode DE and the organic semiconductor layer 50. Theorganic semiconductor layer 50 may include an organic material havinghigh flexibility and conductivity such as pentacene, and may serve as anactive pattern of the organic thin film transistor T.

The organic semiconductor layer 50 may be easily formed by spraying theorganic semiconductor 51 toward the substrate 10 since the non-surfacetreatment section 21 of the gate insulating layer 20 has a surfaceenergy greater than that of the peripheral section.

Referring again to FIG. 5B, since the third insulating layer pattern 42is surface-treated through the surface treatment process, the thirdinsulating layer pattern 42 has a surface energy lower than that of thenon-surface treatment section 21. Thus, attraction between thenon-surface treatment section 21 and the organic semiconductor 51 isgreater than between the third insulating layer pattern 42 and theorganic semiconductor 51. Consequently, although the dispenser 52 maynot exactly (directly) spray the organic semiconductor 51 onto thesecond and third areas A2 and A3, the organic semiconductor 51 may move(gravitate) towards the non-surface treatment section 21 withoutremaining around the second and third areas A2 and A3, such as the thirdinsulating layer pattern 42.

As a result, when forming the organic semiconductor layer 50 by sprayingthe organic semiconductor 51, since the organic semiconductor 51 isrealigned by the surface energy difference, the process of spraying theorganic semiconductor 51 toward the substrate 10 may be performed with asufficient margin.

Referring to FIGS. 9A and 9B, after forming an interlayer dielectriclayer 60 on the substrate 10 on which the organic semiconductor layer 50is formed, a pixel electrode PE may then be formed on the interlayerdielectric layer 60. The pixel electrode PE may be electricallyconnected to the drain electrode DE through a contact hole formedthrough the interlayer dielectric layer 60.

The pixel electrode PE is formed in a pixel area defined in thesubstrate 10. Although not shown in detail in FIGS. 9A and 9B, the pixelarea is defined by the gate line GL and the data line DL that cross eachother. A plurality of pixel areas is defined in proportion to the numberof the gate and data lines GL and DL formed on the substrate 10. Thepixel electrode PE is formed in each pixel area.

Hereinafter, the final structure of the display substrate manufacturedby a manufacturing method of the display substrate according to one ormore embodiments of the present invention will be described in moredetail with reference to FIGS. 9A and 9B.

The gate line GL and the data line DL are formed on the substrate 10 andare insulated from each other by interposing the gate insulating layer20 therebetween. The gate line GL crosses the data line DL, therebydefining the pixel area. Furthermore, the pixel electrode PE is formedin each pixel area. Although the pixel area is not shown in FIGS. 9A and9B, the pixel area may be regarded (considered) as an area in which thepixel electrode PE is formed.

An organic thin film transistor T electrically connected to the pixelelectrode PE is formed in the pixel area. The organic thin filmtransistor T includes the gate electrode GE branching from the gate lineGL, the source electrode SE branching from the data line DL, the drainelectrode DE, which includes material the same as that of the data lineDL, and the organic semiconductor layer 50.

Referring to FIGS. 2A to 7B, the data line DL, the source electrode SEand the drain electrode DE may be made by forming the first conductivelayer 31 on the substrate 10, forming the second conductive layer 34 onthe first conductive layer 31, and then patterning the first and secondconductive layers 31 and 34. Thus, the data line DL, the sourceelectrode SE and the drain electrode DE include the first conductivelayer 31 and the second conductive layer 34 that is laminated on thefirst conductive layer 31.

The source electrode SE includes the bottom source electrode 33 a, whichincludes material the same as that of the first conductive layer 31, andthe top source electrode 36 a, which includes material the same as thatof the second conductive layer 34. The drain electrode DE includes thebottom drain electrode 33 b, which includes material the same as that ofthe first conductive layer 31, and the top drain electrode 36 b, whichincludes material the same as that of the second conductive layer 34.

Furthermore, since the second conductive layer 34 may be removed fromthe area in which the source electrode SE, the drain electrode DE andthe organic semiconductor layer 50 overlap each other, the top sourceelectrode 36 a may have a shape different than that of the bottom sourceelectrode 33 a when viewed in a plan view, and the top drain electrode36 b may have a shape different than that of the bottom drain electrode33 b when viewed in a plan view. The reason for removing the secondconductive layer 34 from the area in which the organic semiconductorlayer 50 is formed is because the contact resistance between the firstconductive layer 31 and the organic semiconductor layer 50 is lower thanthe contact resistance between the second conductive layer 34 and theorganic semiconductor layer 50.

As described above, each of the data line DL, the source electrode SEand the drain electrode DE may include the first conductive layer 31 andthe second conductive layer 34 formed on the first conductive layer 31in an area in which the organic semiconductor layer 50 is not formed.Since the second conductive layer 34 may be removed from the area inwhich the organic semiconductor layer 50 is formed, each of the sourceelectrode SE and the drain electrode DE may include only the firstconductive layer 31 in such area in which the organic semiconductorlayer 50 is formed.

The material of the second conductive layer 34 may be selected such thatthe contact resistance between the second conductive layer 34 and theorganic semiconductor layer 50 is low. Since the top source electrode 36a may have a shape identical to that of the bottom source electrode 33 awhen viewed in a plan view, the top source electrode 36 a may makecontact with the organic semiconductor layer 50. In addition, since thetop drain electrode 36 b may have a shape identical to that of thebottom drain electrode 33 b when viewed in a plan view, the top drainelectrode 36 b may also make contact with the organic semiconductorlayer 50.

Furthermore, the insulating layer pattern 42 may be formed on the dataline DL, the source electrode SE and the drain electrode DE. Theinsulating layer pattern 42 may be located on the same plane with thedata line DL, the source electrode SE and the drain electrode DE in anarea in which the organic semiconductor layer 50 is not formed. As aresult, the second conductive layer 34 and the insulating layer pattern42 may be located on the same plane.

The organic semiconductor layer 50 may partially overlap the sourceelectrode SE and the drain electrode DE, and face the gate electrode GEwhile interposing the gate insulating layer 20 therebetween. The organicsemiconductor layer 50 may include an organic material having highflexibility and conductivity such as pentacene, and may serve as theactive pattern of the organic thin film transistor T.

A portion of the gate insulating layer 20 corresponding to an area inwhich the organic semiconductor layer 50 is formed may have a surfaceenergy greater than that of the insulating layer pattern 42. Referringagain to FIGS. 5A and 5B, when a portion is defined as a non-surfacetreatment section 21, the non-surface treatment section 21 is notsurface-treated by the first preliminary conductive pattern 32 during,for example, the plasma treatment process for the substrate 10. Thus,the non-surface treatment section 21 may have a surface energy greaterthan that of the insulating layer pattern 42 and the gate insulatinglayer 20, which are exposed to the exterior.

The interlayer dielectric layer 60 that covers the organic thin filmtransistor T is formed on the substrate 10, and a contact hole is formedthrough the interlayer dielectric layer 60 such that the top drainelectrode 36 b is exposed. Further, the pixel electrode PE is formed onthe interlayer dielectric layer 60, and is electrically connected to thetop drain electrode 36 b through the contact hole.

According to embodiments of the display substrate and the method ofmanufacturing the display substrate, when forming the organicsemiconductor layer through an inkjet method, the bank pattern used forthe organic semiconductor layer may be omitted. Accordingly, aphotolithography process for the bank pattern may also be omitted, sothat the manufacturing process of the display substrate may besimplified and the manufacturing cost of the display substrate may bereduced.

Although exemplary embodiments of the present invention have beendescribed, it is understood that the present invention should not belimited to these exemplary embodiments but various changes andmodifications can be made by one ordinary skilled in the art within thespirit and scope of the present invention as hereinafter claimed.

1. A display substrate comprising: a substrate in which a pixel area isdefined; a gate line formed on the substrate; a gate insulating layerformed on the substrate to cover the gate line; a data line insulatedfrom the gate line while crossing the gate line, wherein the data linein combination with the gate line define the pixel area; a gateelectrode branching from the gate line; a source electrode branchingfrom the data line; a drain electrode spaced apart from the sourceelectrode; an organic semiconductor layer formed on the source electrodeand the drain electrode; and a pixel electrode formed on the substratein correspondence with the pixel area, and electrically connected to thedrain electrode, wherein a portion of the gate insulating layercorresponding to an area in which the organic semiconductor layer isformed has a surface energy greater than a surface energy of the gateinsulating layer corresponding to an area in which the organicsemiconductor layer is not formed.
 2. The display substrate of claim 1,wherein the portion of the gate insulating layer corresponding to anarea, in which the organic semiconductor layer is formed, does notcomprise fluorine.
 3. The display substrate of claim 1, wherein thesubstrate further comprises glass or plastic.
 4. The display substrateof claim 1, wherein the organic semiconductor layer comprises pentacene.